This invention relates to clock signal distribution systems. More particularly, this invention relates to clock signal distribution systems with reduced parasitic loading effects.
System clock signals are typically remotely generated for distribution to various digital circuit subsystems. The system clock generator and the digital subsystems may be located in geographically disparate regions of the digital circuit. Clock signals are distributed throughout the digital circuit over traces (i.e., device interconnects; e.g., a signal wire) having characteristic parasitic capacitances. The parasitic capacitances result in loading effects (e.g., power loss and effects associated with clock jitter) that can vary in direct proportion to both clock frequency and trace length. Technology trends indicate that the physical separation of system clock generators and associated digital sub-systems will increase as digital circuits become progressively more complex, thereby resulting in increased parasitic load. Moreover, the effects of parasitic loading in digital systems are further exacerbated by ever-increasing system clock frequency.
In view of the foregoing, it would be desirable to provide clock signal distribution systems with reduced parasitic loading effects.